Search Results for author:
Found 4 papers, 2 papers with code
DeFT: Decoding with Flash Tree-attention for Efficient Tree-structured LLM Inference
Given the increasing demand for tree-structured interactions with LLMs, we introduce DeFT (Decoding with Flash Tree-Attention), an IO-aware tree attention algorithm tailored for tree-structured inference.
MARS: Exploiting Multi-Level Parallelism for DNN Workloads on Adaptive Multi-Accelerator Systems
Along with the fast evolution of deep neural networks, the hardware system is also developing rapidly.
Benchmarking High Bandwidth Memory on FPGAs
FPGAs are starting to be enhanced with High Bandwidth Memory (HBM) as a way to reduce the memory bandwidth bottleneck encountered in some applications and to give the FPGA more capacity to deal with application state.
Hardware Architecture
Accelerating Generalized Linear Models with MLWeaving: A One-Size-Fits-All System for Any-precision Learning (Technical Report)
Learning from the data stored in a database is an important function increasingly available in relational engines.
